University of California, Santa Barbara, US
Design of CMOS Annealing Processor for Solving Combinatorial Optimization Problems
Bongjin Kim received his PhD degree from the University of Minnesota in 2014. After his PhD, he worked on design techniques and methodologies for communication circuits and microarchitectures at Rambus and Stanford University as a senior staff and a postdoctoral research fellow. After working as an assistant professor at Nanyang Technological University in Singapore for three years (from 2017 to 2020), he joined the Department of Electrical and Computer Engineering at UC Santa Barbara. His research team develops innovative integrated circuits and system solutions using traditional CMOS logic and emerging technologies to solve challenging problems in fundamental science and accelerate computations and communications. Target applications include, but not limited to, artificial intelligence, machine learning, robotics, and alternative computing. He received the Doctoral Dissertation Fellowship Award at the University of Minnesota and the ISLPED International Low Power Design Contest Award. His research works have been published in peer-reviewed conferences and journals, including the International Solid-State Circuits Conference (ISSCC), VLSI Symposium, Custom Integrated Circuits Conference (CICC), and Journal of Solid-State Circuits (JSSC). He has served on the technical program committee for Design Automation Conference (DAC) and the IEEE Solid-State Circuits Letter (SSC-L) editorial review board.
Annealing processors based on the convergence property of the Ising model offer an attractive means for solving non-deterministic polynomial-time hard (NP-hard) combinatorial optimization problems. Quantum annealing processors exploiting quantum tunneling effect implemented >1K spins using 100K+ Josephson junctions. However, the practical application of quantum annealers is limited due to the extreme operating conditions (e.g., extremely low operating temperature, 15mK) and the associated huge power consumption (e.g., 25kW) as well as high development and operation cost. Alternatively, low-power annealing processors based on simulated annealing have been developed using low-cost CMOS process. This tutorial introduces fundamentals and recent progresses in the design of CMOS annealing processors.