Tutorial Session

June 6, 2021 12:00-12:30 PM (UCT-4)

Only a Q&A session, talks will be online availalbe. we wont play them during the conference.

Bongjin Kim

University of California, Santa Barbara, US

Design of CMOS Annealing Processor for Solving Combinatorial Optimization Problems

Bongjin Kim received his PhD degree from the University of Minnesota in 2014. After his PhD, he worked on design techniques and methodologies for communication circuits and microarchitectures at Rambus and Stanford University as a senior staff and a postdoctoral research fellow. After working as an assistant professor at Nanyang Technological University in Singapore for three years (from 2017 to 2020), he joined the Department of Electrical and Computer Engineering at UC Santa Barbara. His research team develops innovative integrated circuits and system solutions using traditional CMOS logic and emerging technologies to solve challenging problems in fundamental science and accelerate computations and communications. Target applications include, but not limited to, artificial intelligence, machine learning, robotics, and alternative computing. He received the Doctoral Dissertation Fellowship Award at the University of Minnesota and the ISLPED International Low Power Design Contest Award. His research works have been published in peer-reviewed conferences and journals, including the International Solid-State Circuits Conference (ISSCC), VLSI Symposium, Custom Integrated Circuits Conference (CICC), and Journal of Solid-State Circuits (JSSC). He has served on the technical program committee for Design Automation Conference (DAC) and the IEEE Solid-State Circuits Letter (SSC-L) editorial review board.

Annealing processors based on the convergence property of the Ising model offer an attractive means for solving non-deterministic polynomial-time hard (NP-hard) combinatorial optimization problems. Quantum annealing processors exploiting quantum tunneling effect implemented >1K spins using 100K+ Josephson junctions. However, the practical application of quantum annealers is limited due to the extreme operating conditions (e.g., extremely low operating temperature, 15mK) and the associated huge power consumption (e.g., 25kW) as well as high development and operation cost. Alternatively, low-power annealing processors based on simulated annealing have been developed using low-cost CMOS process. This tutorial introduces fundamentals and recent progresses in the design of CMOS annealing processors.

Siegfried Karg

IBM Research Zurich, Switzerland

Computing with Oscillating Neural Networks

Dr. Siegfried Karg is a Research Staff Member at IBM Research – Zurich and a Senior Member of IEEE. He worked on the physics and materials science of organic and polymer devices (OLEDs, OFETs and electrochemical cells). He has conducted research on memory applications such as resistive oxide RAM and on capacitorless eDRAM based on III-V semiconductor transistors. Moreover, he investigated the one-dimensional electronic properties of InAs nanostructures. His current research fields include brain-inspired computing applications exploiting oscillatory neural networks (with electronic oscillators based on the metal-insulator transition of VO2). S. Karg has authored about 100 scientific publications and holds more than 30 patents.

Machine-learning applications are penetrating virtually every aspect of modern society, e.g. natural-language processing for virtual personal assistants, image recognition for social media, mobility data for traffic prediction. Nonetheless, already fairly simple tasks in human everyday life such as recognizing patterns from a stream of images brings even the most powerful computer chip at its limits. The underlying von-Neumann architecture with its physically separated processor and memory appears as a major bottleneck for faster and more power-efficient inference machines. In-memory or in-sensor computation has been proposed to reduce data traffic and latency. This offers the opportunity to move specific tasks into the analog domain and process data inherently parallel and power efficient. However, these neuromorphic computing approaches come with substantial challenges for system design, mixed-signal electronic circuits and physical modelling.

Development of materials with non-linear properties such as memristive oxides or metal-insulator transition materials offer new routes to brain-inspired data processing. As an example, we will show a novel and alternative neuromorphic computing paradigm based on oscillating neural networks (ONN). Area and power efficient relaxation oscillators based on the metal-insulator phase-transition material VO2 act as ‘neurons’. Tunable memristors are envisioned as the ‘synapses’ of the network. Inspired by neural oscillations or brain waves, in ONN the information is encoded in the phase of coupled oscillators.

We will demonstrate the neuro-computational computing power of these phase-modulated ONN by means of experiments and simulations. The scope of the project ranges from material and fabrication aspects of VO2 layers, over device fabrication and characterization and modelling to circuit-level ONN implementations and simulation of ML applications. Key questions on topics such as influence of device and process variability, prospects of the ONN architecture for compute performance and power consumption will be addressed.

Abhronil Sengupta

The Pennsylvania State University, US

Neuromorphic Computing – Opportunities and Challenges

Dr. Abhronil Sengupta is an Assistant Professor in the School of Electrical Engineering and Computer Science at Penn State University. He is also affiliated with the Department of Materials Science and Engineering and the Materials Research Institute (MRI). Dr. Sengupta received the PhD degree in Electrical and Computer Engineering from Purdue University in 2018 and the B.E. degree from Jadavpur University, India in 2013. He worked as a DAAD (German Academic Exchange Service) Fellow at the University of Hamburg, Germany in 2012, and as a graduate research intern at Circuit Research Labs, Intel Labs in 2016 and Facebook Reality Labs in 2017. Dr. Sengupta has published over 60 articles in referred journals and conferences and holds 4 granted/pending US patents. He serves on the IEEE Circuits and Systems Society Technical Committee on Neural Systems and Applications, Editorial Board of Neuromorphic Computing and Engineering, Frontiers in Neuroscience journals and the Technical Program Committee of several international conferences like DAC, ICCAD, ISQED and GLSVLSI. He has been awarded the IEEE Circuits and Systems Society (CASS) Outstanding Young Author Award (2019), IEEE SiPS Best Paper Award (2018), Schmidt Science Fellows Award nominee (2017), Bilsland Dissertation Fellowship (2017), CSPIN Student Presenter Award (2015), Birck Fellowship (2013), the DAAD WISE Fellowship (2012). His work on neuromorphic computing has been highlighted in media by MIT Technology Review, US Department of Defense, American Institute of Physics among others. Dr. Sengupta is a member of the IEEE Electron Devices Society (EDS) and Circuits and Systems (CAS) Society, the Association for Computing Machinery (ACM) and the American Physical Society (APS).

While research in designing brain-inspired algorithms have attained a stage where such Artificial Intelligence platforms are being able to outperform humans at several cognitive tasks, an often-unnoticed cost is the huge computational expenses required for running these algorithms in hardware. Bridging the computational efficiency gap necessitates the exploration of devices, circuits and algorithms that provide a better match to the computational primitives of biological processing – neurons and synapses, and which require a significant rethinking of traditional von-Neumann based computing. The tutorial will discuss innovations in emerging post-CMOS technologies that are revealing immense possibilities of implementing a plethora of neural and synaptic functionalities by single device structures that can be operated at very low terminal voltages. The tutorial will also discuss recent innovations at the algorithm front on exploring event-driven Spiking Neural Networks for large-scale machine learning tasks. Such neuromorphic systems can potentially provide significantly lower computational overhead in contrast to standard deep learning platforms, especially in sparse, event-driven application domains with temporal information processing. I will conclude the presentation by providing the prospects of enabling end-to-end cognitive intelligence across the computing stack that combines knowledge from devices and circuits to machine learning and computational neuroscience.

Théophile Gonos

A.I.Mergence, France

Artificial Intelligence & Robotics Design challenges and perspectives

Théophile Gonos received a PhD degree from the School of “Informatics” of the University of Edinburgh (UK) in 2011, for his work on bioinspired adaptive sensing. He also received an MSc degree in Robotics and Intelligent Systems from UPMC (Paris-Sorbonne) and a BSc degree in Computer Science from Denis Diderot University, Paris. His fields of expertise in Artificial Intelligence are on multi-agent systems, modular robotics, as well as bioinspired systems and neural networks. He founded the company A.I.Mergence in 2015, which is developing an autonomous safety robot named E4, aiming to ensure indoor security.

Robotics and Artificial Intelligence are part of a technological revolution in nowadays human society. But many constrains are raised by the specific needs of robotics in hardware – motors, batteries, sensors – as well as in software, framework compatibilities for instance. Robotic systems development also needs a multiple-skill team and a good communication between different parts of the field: mechanics, electronics, and computer science.

Moreover, despite the recent development, power consumption and computational capabilities remain a major bottleneck of robotics advances. Legal aspects also need to be addressed such as responsibility of robots or more recently the European legislation such as RGPD.

On the contrary, for the past several years, the development of smartphones and IoT devices have increased the computational capabilities and drastically reduced the power consumption of embedded chips. More specifically, a current line of research focuses on designing bio-inspired low-energy AI chips.

In this talk we address the main challenges that a company needs to cope with to build robotic and embedded systems. Throughout the talk, we will use the company’s robot E4 as a study case, designed to ensure building protection. We will also briefly address cultural and social threats for creating such devices and speak about market perspectives.