Keynote Speakers

Shaojun Wei

Tsinghua University, China

June 6, 2021 09:00-09:45 AM (UCT-4)

Software-defined AI Chip – with the Emphasis on Architecture Innovation

Dr. Shaojun Wei graduated from the Department of Radio & Electronics of Tsinghua University, China, in 1984 and received his Master degree in engineering. He received his Doctor degree in Applied Science from the Faculté Polytechnique de Mons (FPMs), Belgium, in 1991.

Dr. Shaojun Wei is now the professor of Tsinghua University; Chief Scientist of the State Key Science and Technology Project; Member of the National Integrated Circuit Industry Development Advisory Committee; Vice President of China Semiconductor Industry Association (CSIA) and President of Fabless Chapter CSIA. Dr. Wei was the President & CEO of Datang Telecom Technology Co., Ltd. and the CTO of Datang Telecom Industry Group between 2001-2006.

Dr. Wei has been working on VLSI design methodologies research and reconfigurable computing technology research. He has published more than 200 peer-reviewed papers and 6 monographs. He owns more than 130 patents including 18 US patents. Dr. Wei is the Fellow of Chinese Institute of Electronics (CIE) and the IEEE Fellow.

Dr. Wei had won many awards including China National Second Award for Technology Invention (2015), China National Second Award for Technology Progress (2001), SIPO & WIPO Patent Golden Award (2003, 2015), First Award for Science and Technology of Ministry of Education (2014, 2019), China, First Award for Technology Invention of CIE (2012, 2017), EETimes China IC Design Achievement Award (2018), Aspencore Outstanding Contribution Award of the Year/Global Electronic Achievement Awards (2018) and SEMI Special Contribution Award (2019) and etc. He was selected to be the recipient of the 2020 IEEE CAS Industrial Pioneer Award.

Over the past decades, Application Specific Integrated Circuit (ASIC) is employed to meet specific system requirements. A wide variety and small volume are the advantages of ASIC. However, the diversity of applications contradicts the high investment in ASIC R&D while process technology going to 1Xnm. To realize an ASIC corresponding to the application in a low-cost way, a hardware scheme with the same topology as the C/C++ description should be the most direct implementation and the most efficient as well. Reconfigurable chip is both software and hardware programable. The hardware architecture and functions change dynamically in real-time with the change of software algorithm while ensuring flexibility. Thus it is also called a software-defined chip. The wide adaptability of the software-defined chip makes it a strong competitor to replace ASIC, FPGA, and general-purpose processors.

Artificial intelligence (AI) is ubiquitous and AI chip has become a research hotspot in recent years. AI algorithms vary in different applications and will continue to evolve. AI services are migrating from cloud to edge nowadays. Performance demands and power consumption constraints require AI to deployed on an energy-efficient computing engine. Reconfigurable architecture is the ideal solution for intelligent computing since its programmability and dynamic reconfigurability of architecture can adapt algorithm evolution and diversity of applications and greatly improves energy efficiency as well.

Dynamically reconfigurable technology brings the ability to bear the diversity and evolution of AI algorithms. Software-defined AI chips are expected to provide a new route for China's chip technology to get rid of imitation.

Ram K. Krishnamurthy

Intel Corporation, US

June 6, 2021 09:50-10:35 AM (UCT-4)

High-performance and energy-efficient circuit technologies for sub-5nm in-memory/near-memory AI accelerators

Ram K. Krishnamurthy received the B.E. degree in electrical engineering from the National Institute of Technology, Trichy, India, in 1993, the M.S. degree in electrical and computer engineering from the State University of New York, Buffalo, NY, USA, in 1994, and the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 1997. He has been at Intel Corporation since 1997. He is currently a Senior Research Director and Senior Principal Engineer at Intel Labs, Hillsboro, OR, USA, where he heads the High Performance and Low Voltage Circuits Research Group. In this role, he leads research in high performance, energy-efficient, and low-voltage circuits for next generation microprocessors, accelerators, and Systems-On-Chip (SoCs). He has led circuit technology research directions in high speed arithmetic units, on-chip interconnects, reconfigurable computing, energy efficient clocking, ultra low voltage design, hardware security, compute-in-memory, neuromorphic computing, and machine learning accelerators. He has made circuit technology contributions to multiple generations of Intel’s data center, client, FPGA, IoT, and AI products spanning across 180nm to 7nm process technology nodes. Krishnamurthy has filed 320 patents and holds 180 issued patents. He has published 200 papers and four book chapters on high-performance and energy-efficient circuits. He serves as the Chair of the Semiconductor Research Corporation (SRC) Technical Advisory Board for the circuit design thrust. He served as the Technical Program Chair and the General Chair of the IEEE International Systems-on-Chip Conference and presently serves on the Conference’s Steering Committee. He is an Adjunct Faculty with the Electrical and Computer Engineering Department, Oregon State University, Corvallis, OR, USA, where he taught advanced VLSI design. Krishnamurthy has received two Intel Achievement Awards for pioneering the first 64-bit Sparse-Tree ALU Technology and the first Advanced Encryption Standard hardware security accelerator on Intel products. He has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award, IEEE European Solid State Circuits Conference Best Paper Award, Outstanding Industry Mentor Award from SRC, Intel awards for most patents filed and most patents issued, Intel Labs Gordon Moore Award, Alumni Recognition Award from Carnegie Mellon University, Distinguished Alumni Award from the State University of New York, MIT Technology Review’s TR35 Innovator Award, and was recognized as a top ISSCC paper contributor. He has served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, a Guest Editor of the IEEE Journal of Solid State Circuits, an Associate Editor of the IEEE Transactions on VLSI Systems, and on the Technical Program Committees of ISSCC, CICC, and SOCC conferences. He is a Fellow of the IEEE and a Board Member of the Industry Advisory Board for the State University of New York.

This presentation will highlight some of the emerging challenges and opportunities for sub-5nm process machine learning and AI technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-5nm technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

Vikas Chandra

Facebook, US

June 7, 2021 09:00-09:45 AM (UCT-4)

On-device AI for Augmented Reality (AR) Systems: Challenges and Opportunities

Vikas Chandra leads the On-device AI applied research and engineering organization at Facebook Reality Labs responsible for developing real-time on-device computer vision, machine perception and speech/NLU technologies across AR/VR products. He received his Ph.D. in Computer Engineering from Carnegie Mellon University in 2004. He has held the positions of Visiting Scholar (2011 – 2014) and Visiting Faculty (2016 – 2017) at Stanford University. Dr. Chandra has authored 80+ research publications and is an inventor on 40+ US and international patents. He received the ACM-SIGDA Technical Leadership Award in 2009 and was invited to the 2017 National Academy of Engineering’s Frontiers of Engineering Symposium. He is a senior member of IEEE. His research interests include all aspects of SW/HW co-design for efficient On-device AI.

Augmented reality (AR) is a set of technologies that will fundamentally change the way we interact with our environment. It represents a merging of the physical and the digital worlds into a rich, context aware user interface delivered through a socially acceptable form factor such as eyeglasses. The majority of these novel experiences in AR systems will be powered by AI because of their superior ability to handle in-the-wild scenarios. In this presentation, we will discuss the challenges and opportunities in enabling AI-based algorithms in an energy-constrained AR system. One key AR use case is a personalized, proactive and context-aware Assistant that can understand the user’s activity and their environment using audio-visual understanding. In this presentation, we will discuss the challenges and opportunities in both training and deployment of efficient audio-visual understanding on AR glasses. We show why it is imperative to co-design and co-optimize the AI algorithms and the hardware platforms jointly. We will present our early work to demonstrate the benefits and potential of such a co-design approach and discuss open research areas that are promising for the research community to explore.

Young-Kai (Y.K.) Chen

Defense Advanced Research Projects Agency(DARPA), US

June 8, 2021 09:00-09:45 AM (UCT-4)

Emerging AI Processing for Wireless Applications

Dr. Young-Kai (Y.K.) Chen, is a Program Manager with the Microsystems Technology Office at DARPA. Before joined DARPA in September 2017, he was a Senior Director at Nokia Bell Labs supporting research groups to develop high speed electronics and optoelectronics for advanced wireless and optic fiber communication networks. Dr. Chen and his teams had contributed to first commercial integrated DFB-EAM devices, silicon-based frontend ICs for 3G/4G/5G millimeter-wave backhaul radios, and launched the first commercial 100Gbps optical transponders in 2011. His team also developed silicon photonics ICs for microwave photonics and 100G data links.

Dr. Chen received his Ph.D. degree from Cornell University. He was an Adjunct Professor at Columbia University, National Taiwan University and National Chiao-Tung University. Dr. Chen is a Fellow of Bell Labs, IEEE and OSA, a member of the Academia Sinica and National Academy of Engineering, and a recipient of IEEE David Sarnoff Award and Edison Patent Award.

The emerging artificial intelligence and machine learning techniques promise new solutions and capabilities to unify the human world with the physical world and digital world together. This talk will illustrate a few challenges and solutions on utilizing artificial intelligence to enable next generation wireless communications.

Yen-Kuang Chen

Alibaba Group, US

June 9, 2021 09:00-09:45 AM (UCT-4)

AI and Video Compression in the Era of Internet of Video Things

Yen-Kuang Chen received his Ph.D. degree from Princeton University and is a Senior Director and Chief Scientist of Computing Technology, Computing Technology Lab, DAMO Academy, Alibaba. His research areas span from emerging applications that can utilize the true potential of multimedia and Internet of Things (IoT) to computer architecture that can embrace emerging applications. He has 80+ US patents and 100+ technical publications. He is one of the key contributors to Supplemental Streaming SIMD Extension 3 and Advanced Vector Extension in Intel microprocessors. He is recognized as an IEEE Fellow for his contributions to algorithm-architecture co-design for multimedia signal processing.

We are at the very beginning of the era of Internet of Video Things (IoVT), where many cameras collect a huge amount of visual data to be analyzed. IoVT will become more important as the numbers of cameras and applications are growing exponentially in the coming years. Humans cannot process all the videos and it is critical to use artificial intelligence (AI) to process the data. Many challenges arise fulfilling the era of IoVT, e.g., accuracy, energy efficiency, processing speed. This talk will discuss the following question: Can we design efficient IoVT systems by co-optimizing video compression and computer vision algorithms?